1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a countermeasure method against NBTI degradation.
2. Description of the Related Art
In a flip-flop circuit included in a semiconductor integrated circuit device, when a high-level or low-level fixed value is input in a low power consumption mode, there is a part in a circuit where a fixed-value negative bias voltage is applied to a gate electrode of a P-channel metal oxide semiconductor (PMOS) transistor. In such a PMOS transistor applied with the fixed-value negative bias voltage, electric current does not flow and the PMOS transistor becomes an ON state. When this situation is repeated, a degradation phenomenon referred to as negative bias temperature instability (NBTI) occurs. In addition, in a logic circuit to which an output of the flip-flop circuit is input, because a high-level or low-level fixed value output from the flip-flop circuit is transmitted under the above circumstances, the fixed-value negative bias voltage can be applied to the gate electrode of the PMOS transistor in the logic circuit. If the fixed-value negative bias voltage is actually applied thereto, the PMOS transistor in the logic circuit simply becomes an ON state without any current flow, and therefore deterioration due to NBTI similarly occurs in the PMOS transistor in the logic circuit.
The NBTI is a degradation phenomenon (change with time passage) that tends to occur with downsizing of PMOS transistors and development of low-voltage PMOS transistors. That is, the NBTI is a phenomenon such that when a PMOS transistor is maintained simply in an ON state without any current flowing in a certain temperature environment, and when an electric field having high field strength is applied to a gate oxide film, electric charge is captured by a shallow trap of a low energy level formed in the gate oxide film, and as a result, a threshold voltage of the PMOS transistor is raised and biased to a negative side. When the threshold voltage shifts to the negative side, a drive current (drain current) at the time of an operation of the PMOS transistor used by flowing current decreases, thereby causing a problem of performance degradation.
When a data path in the flip-flop circuit is degraded due to NBTI in a low power consumption mode, a setup time margin of the flip-flop circuit decreases at the time of operating in a normal operation mode. Further, when NBTI degradation occurs in a clock path, an erroneous operation due to clock skew occurs because a delay variation amount due to the degradation is different in each path.
Conventionally, therefore, a timing analysis is performed in a low power consumption mode as measures against NBTI at the time of designing, and a library for a timing adjusting cell is designed, taking into consideration a time margin after NBTI degradation.
However, in a designing method taking the time margin after NBTI degradation into consideration, an over margin is generated. This causes problems such that a circuit size increases to incur cost increase, circuit characteristics deteriorate due to interruption of a high-speed operation, and further cost increase is incurred due to a prolonged development period.
Meanwhile, as a designing method not taking a time margin after NBTI degradation into consideration, for example, there are techniques disclosed in JP-A 2006-109091 (KOKAI) and JP-A 2006-211494 (KOKAI). However, these patent applications only disclose a technique for preventing the occurrence of erroneous operations due to clock skew mentioned above, and do not disclose measures against performance degradation due to NBTI degradation in a data path in a flip-flop circuit.